1. Field of the Invention
The present invention generally relates to integrated circuit packaging and, more particularly, to the provision of module and package designs of increased economy of manufacture and increased chip connection density.
2. Description of the Prior Art
It has been recognized that increased device (e.g. transistors, capacitors and the like) density in integrated circuits yields substantial performance benefits as well as manufacturing economies. The increased proximity of devices leads to improvements in noise immunity while decreasing signal propagation time between devices. Increased numbers of devices per chip leads to increases in reliability, manufacturing yield and functionality of chips operating at reduced voltage to reduce power. Economies in manufacture derive from the development of greater numbers of devices with a given sequence of manufacturing process steps. Similar benefits are derived from packaging chips more compactly in modular packages, sometimes including and providing connections between hundreds of discrete chips in a single modular package.
These pressures toward increased integration density of integrated circuit chips and the development of new technologies in support thereof have established a trend which now leads to an expectation of 100% increase in integration density, 30% reduction in operating voltage and 20% increase in performance every eighteen months. However, increases in functionality of integrated circuit chips cannot be exploited without provision of adequate signal input and output (I/O) communication paths to and from the chip(s). Further, substantial power must be supplied thereto and power distribution on the chip consumes valuable space and may compromise reliability of fine connections through mechanisms such as metal migration in narrow and closely spaced conductors subjected to large temperature excursions. Further, multiple supply voltages are currently employed to manage power consumption and dissipation requirements of chips and to provide interface voltage compatibility with other chip technologies.
It is also convenient to generally standardize connection dimensions for both signals and power to simplify connection techniques (e.g. using solder preforms) and the current which can be carried by each connection is limited. Therefore, it is not uncommon for one-quarter to one-third of all connections to a chip to be dedicated to power supply or ground connections. Since a minimum spacing of connections must be provided, the number of power connections restrict the number of signal connections that can be made to a chip of a given area.
These trends and conflicting limitations apply to both production integrated circuit packages having more-or-less standardized designs such as processors, memories, memory controllers and the like, some of which are collectively referred to as chip sets, and to so-called application specific integrated circuits (ASICs) which are manufactured to a customer's specifications of function but generally utilize a standardized interface (e.g. pin-out) hardware and other industry standard specifications so that the amount of customized hardware can be held to a minimum to minimize customer costs in constructing the equipment in which ASICs may be employed.
For this reason, some design criteria are more difficult to meet for ASICs than for production integrated circuits. Since ASICs are, by their nature, custom-fabricated devices they are expensive and the I/O requirements must be designed with a view to the requirements and economy of production of the equipment in which they are to be used. Therefore, it is common practice to design I/O connections to make maximal use of standard integrated circuit hardware to support the functions of the ASICs to the limit imposed by overall custom function and physical requirements.
While production integrated circuits can be increased in scale to reduce pin-out numbers (theoretically to multi-byte input, output and control ports and a single power supply) such an approach in an ASICs design where the cost can only be amortized over a relatively small number of packages may be prohibitively expensive. Accordingly, increased chip functionality almost invariably leads to increased number of required I/O connections in ASICS, often referred to as Rents Rule, to allow the functions provided by an ASIC to communicate with circuits which are off the chip.
Merely increasing chip size or connection density or utilizing the entire chip footprint, which have been the traditional approaches to date, does not provide a viable solution to the need for increased connections to ASIC chips or packages at the present state of the art. As alluded to above, non-standard or custom connection patterns increase the cost of manufacture of ASICs and devices which include them even if the change is within the capability of a mature technology. Non-standard hardware can also greatly increase costs. Development of new technologies to accommodate custom ASIC designs would almost necessarily be prohibitive in cost and would greatly delay delivery time as well as raise unacceptable uncertainties in regard to delivery dates and the capacity of a manufacturer to deliver the ASICs according to the specified design.
In regard to the packaging of integrated circuit chips, a problem is presented by the need to provide wiring from individual chip connections generally provided at a very fine pitch to pin or connection locations on the package where connections are made from the package to a circuit board or other support structure. These latter connections are generally provided at a much more coarse pitch than connections on a chip which are too closely spaced for a suitably robust conductor to be passed between.
Therefore, a number of layers of connections are necessary in the chip package to provide an array of suitable wiring connections to "escape" the chip. The number of layers of wiring required generally must increase with the number and types (e.g. signals and plural power supplies) of connections which must be made and the complexity of alignment and routing of connections of respective types on respective layers. For example, to escape from a conventional connection pattern shown in FIG. 1 and which will be described in greater detail below, twelve connection layers are required to provide good electrical performance. It can be readily appreciated that the number of layers which must be provided constitutes a significant portion of the package expense.
Conductor routing in the packaging also affects chip performance. Generally, it is common practice to provide a mesh of conductors for each power supply (e.g. V1, V2, Ground) in different levels below the area where the chip or die is to be attached and connected. Another mesh or conductor pattern is generally provided outside the chip or die area and, for current chip connection patterns such as that of FIG. 1, the mesh under the chip is not aligned with and not easily connectable directly to the conductor pattern outside the chip or die area. The additional connection hardware and/or connection length leads to resistive voltage drops and inductive "delta-I" drops and are thus likely sources of noise and ambiguous logic value voltages is which may compromise chip performance.